1 of 8 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 2k x 8 volatile static ram or eeprom ? unlimited write cycles ? low - power cmos ? jedec standard 28 -pi n dip package ? read and write access times of 150 ns ? full 10% operating range ? optional industrial temperature range of - 40c to +85c, designated ind pin assignment 24- pin encapsulated package 720- mil extended pin description a0-a12 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground description the ds1225y 64k nonvolat ile sram is a 65,536 - bit, fully static, nonvolatile ram organized as 8192 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is un conditionally enabled to prevent data corruption. the nv sram can be used in place of existing 8k x 8 sram s directly conforming to the popular bytewide 28 - pin dip stan dard. the ds1225y also matches the pinout of the 2764 eprom or the 2864 eeprom, allowing direct substitution while enhancing perform ance. there is no limit on the number of write cycles that can be executed and no additional support circu itry is required f or micro - processor interfacing. ds1225y 64k nonvolatile sram 19 - 5603; rev 10/10 www.maxim - ic.com 15 13 27 a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 vcc we nc a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq3 dq4 1 2 3 4 5 6 7 8 9 10 11 12 14 28 26 25 24 23 22 21 20 19 18 17 16 a12 a6 a4 nc not recommended for new designs downloaded from: http:///
n ot r ecommended for new designs ds1225y 2 of 8 read mode the ds1225y executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the uniq ue address specified by the 13 address inputs (a 0 -a 12 ) defines which of the 8192 bytes of data is to be accessed. valid data wil l be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providi ng that ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later - occurring signal and the li miting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1225y executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control si gnal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output driver s are enabled ( ce and oe active) then we will disable the outputs in t odw from its fa lling edge. data retention mode the ds1225y provides full functional capability for v cc greater than 4.5 volts and write protects at 4.25 nominal. data is maintained in the absence of v cc without any additional support circuitry. the ds1225y constantly mo nitors v cc . should the supply voltage decay, the nv sram automatically write protects itself, all inputs become dont care, and all outputs become high impedance. as v cc falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operati on can resume after v cc exceeds 4.5 vo lts. downloaded from: http:///
n ot r ecommended for new designs ds1225y 3 of 8 absolute maximum ratings voltage on any pin relative to ground - 0.3v to + 6 .0v operating temperature range commercial: 0 c to +70 c industrial: -40 c to +85 c storage temperature -40 c to +85 c lead temperature (soldering, 10 s) +260c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or an y other conditions above t hose indicated in the operation sections of this specification is not implied. exposure to absolute maximum r ating conditions for extended periods of time ma y affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power supply voltage v cc 4.5 5.0 5.5 v input logic 1 v ih 2.2 vcc v input logic 0 v il 0.0 +0.8 v dc electrical characteristics (t a : see note 10; v cc = 5v 10%) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v 1 ccs1 5 10 ma standby c urrent ce =v cc -0.5v 1 ccs2 3 5 ma operating current t cyc =200ns (commercial) 1 cco1 75 ma operating current t cyc = 200ns (industrial) i cco1 85 ma write protection voltage v tp 4.25 v 10 downloaded from: http:///
n ot r ecommended for new designs ds1225y 4 of 8 ac electrical characteristics (t a : see note 10; v cc =5.0v 10%) parameter symbol ds1225y-150 units notes min max read cycle time t rc 150 ns access time t acc 150 ns oe to output valid t oe 70 ns ce to output valid t co 150 ns oe or ce to output active t coe 5 ns 5 output high z from deselection t od 35 ns 5 output hold from addresschange t oh 5 ns write cycle time t wc 150 ns write pulse width t wp 100 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 0 10 ns ns 12 13 output high z from we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 60 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 capacitance (t a = + 25 c) parameter symbol min typ max units notes input capacitance c in 10 pf input/output capacitance c i/o 10 pf downloaded from: http:///
n ot r ecommended for new designs ds1225y 5 of 8 read cycle see note 1 write cycle 1 see note 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see note 2 , 3, 4, 6, 7, 8 and 13 downloaded from: http:///
n ot r ecommended for new designs ds1225y 6 of 8 power - down/power - up condition see note 11 power - down/power - up timing parameter symbol min max units notes ce at v ih before power - down t pd 0 s 11 v cc slew from v tp to 0v t f 100 s v cc slew from 0v to v tp t r 0 s ce at v ih after power - up t rec 2 ms (t a = + 25 c) parameter symbol min max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds is measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high - impedance state during this period . downloaded from: http:///
n ot r ecommended for new designs ds1225y 7 of 8 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period. 9. each ds1225y is m arked with a 4 - digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0c to 70c. for industrial produc ts (ind), this range is - 40c to +85c. 11. in a power down condition the voltage on any pin may not exceed the voltage o n v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce going high. 14. ds1225y modules are recognized by underwriters laborator ies (u l ) under file e99151 (r). dc test conditions outputs open. all voltages are referenced to ground. ac test conditions output load: 100pf + 1ttl gate input pulse levels: 0 -3.0v timing measurement reference levels input:1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part temp range supply tolerance speed grade (ns) pin - package ds1225y-150+ 0c to +70c 5v 10% 150 28 720 edip ds1225y- 150ind+ - 40c to +85c 5v 10% 150 28 720 e dip + denotes a lead (pb) - free/rohs - compliant p ackage. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs sta tus. package type package code outline no. land pattern no. 28 edip mdt28+2 21-0245 downloaded from: http:///
n ot r ecommended for new designs ds1225y 8 of 8 revision history revision date de scription pages changed 121907 added the p ackage information table ; r emoved the dip module package drawing and dimension table 7 10/10 added not recommended for new designs status; updated the storage information, soldering tem perature, and lead temperature information in the absolute maximum ratings section ; removed the - 170 and - 200 min/max information from the ac electrical characteristics table; added the updated the ordering information table 1, 3, 4, 7 downloaded from: http:///
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